A phase-locked loop (PLL) generates an output clock that the PLL phase locks to an input reference clock. A PLL may include an analog phase-locked loop (APLL) to generate the output clock. The PLL also may include a digital PLL (DPLL). The DPLL includes a time-to-digital converter (TDC) that generates a digital output value that is a function of the phase difference between corresponding edges of the reference clock and a feedback clock derived from the output clock. The digital signal from the TDC is filtered by a digital loop filter and the digital loop filter's output is used to adjust a divide ratio of a frequency divider within the APLL.